The disclosed embodiments of the present invention relate to a decoding scheme, and more particularly, to a decoding apparatus with de-interleaving efforts distributed to different decoding phases (e.g., a linear/sequential decoding phase and an interleaved decoding phase) and related decoding method thereof.
Data signals, in particular those transmitted over a typically hostile channel, are susceptible to channel noise/interference. Various methods of error correction coding have been developed in order to minimize the adverse effects that a hostile channel has on the integrity of the transmitted data. This is also referred to as lowering the bit error rate (BER), which is generally defined as the ratio of incorrectly received information bits to the total number of received information bits. Error correction coding generally involves representing digital data in ways designed to be robust with respect to error bits. Hence, error correction coding may enable a communications system to recover original data from a signal that has been corrupted due to the undesired channel noise/interference.
For example, turbo codes may be used in the communications system, such as a Wideband Code Division Multiple Access (W-CDMA) system, for channel coding. Regarding the turbo coding system, the input data of a data block may be rearranged with an interleaver and then encoded with the same method as that applied to the original input data. In this way, the data block is encoded with a particular coding method, resulting in an encoded data having systematic bits and two sets of parity bits included therein. The encoded data is combined in some manner to form a serial bit stream and transmitted from a turbo encoding apparatus at a transmitter end to a turbo decoding apparatus at a receiver end through the channel. In general, a conventional turbo decoding apparatus uses an iterative algorithm between two soft-input soft-output (SISO) decoders, and therefore exchanges information between the SISO decoders in order to improve error correction performance.
To achieve a higher transmitted data rate, a possible solution is to apply parallel processing for turbo code decoding. For example, the turbo decoding apparatus may use SISO decoders, each having multiple decoder cores, for processing codeword segments simultaneously, thus providing a higher throughput without increasing the clock speed. However, the decoding performance of such a turbo decoding apparatus may be heavily affected by the interleaver design. Regarding a third generation (3G) communications system (e.g., W-CDMA system), a rectangular interleaver with inter-row permutation and intra-row permutation is employed by the turbo decoding apparatus. However, the rectangular interleaver is particularly designed for rich randomness without considering the multi-core turbo decoder implementation at that time. In other words, this parallel processing approach raises a memory contention problem caused by multiple accesses of the same memory bank in a memory device. For example, data bits of a data block to be decoded are sequentially stored into a memory device. Specifically, the data block to be decoded is stored in the memory device without inter-row permutation and intra-row permutation applied thereto. Hence, data bits of the data block to be decoded are stored in memory banks of the memory device in an original successive bit sequence. Regarding the conventional turbo decoder design, a first SISO decoder is arranged to refer to first parity bits of the data block to perform a decoding operation without inter-row de-interleaving and intra-row de-interleaving memory accesses due to the fact that the first parity bits are derived from the non-interleaved input data. However, regarding a second SISO decoder of the decoding apparatus, it is required to refer to second parity bits to perform a decoding operation with inter-row de-interleaving and intra-row de-interleaving memory accesses due to the fact that the second parity bits are derived from an interleaved input data. Hence, when the second SISO decoder is implemented using a multi-core decoder, it is possible that multiple decoder cores may request the desired data bits to be decoded from the same memory bank, which results in memory contention. When the memory contention occurs, only one decoder core is allowed to fetch the requested data bits from a target memory bank, and the remaining decoder cores need to wait. As a result, before the requested data bits are available, the decoding operation performed by the remaining decoder cores is stalled.
In view of the foregoing, there is a need for an innovative contention-free memory access for realizing a high-throughput multi-core turbo decoding apparatus.